I have been working on improving the hardware design of the dynamic clamp system, especially to make the need for calibration less frequent.
The main points are that the new hardware design: (1) uses a 3.3 V voltage reference (https://amzn.to/2TVeD9h) to provide a reference voltage for the circuits of Figures 2B and 2D rather than relying on the output of the rail splitter for this purpose (the rail splitter continues to provide the ± 9 V needed to power the op-amps); (2) includes diodes to protect the Teensy ADC in case of an accidental over-voltage; and (3) rearranges the resistors so that it is simpler to find values that will capture most of the dynamic range of the amplifier and/or digitizer. The main advantage of these changes is that, by using a stable and (relatively) exact 3.3 V as the reference, imperfections in the 18 V power supply (“wall wart”) and some of the other components don’t matter as much. In fact, the system may not need calibration at all.
The new designs affect the circuits of Figure 2B (scaling and shifting the signal coming from the patch clamp amplifier before sending it to the Teensy ADC input), Figure 2D (scaling and shifting the Teensy DAC output to match the range of the command input of the amplifier), and Figure 2E (adding the dynamic clamp command V_DC and the data acquisition board command V_DAQ). Each figure below links to a CircuitLab simulation — just right click and select “Open link in new tab”.
At some point — hopefully soon (I write this in July 2019) — I will modify the other parts of this website to reflect these new designs. At the moment, the other parts reflect the designs of the original paper.